A time-division telephone switching system employing a time-shared space division network and interface circuits having input and output buffer memories and control memories is disclosed in U.S. Pat. No. 3,736,381 of Johnson et al. In order to attain the desired degree of reliability in an independently operating telephone switching system, it is common practice to duplicate the system's critical hardware and to operate such hardware in parallel. Customarily, such hardware is designated to be either in the "active" or "stand-by" mode and only the output information produced by the active units of the system is recognized as the system's output. In the event that an error is detected in an active unit, the roles of the two units are switched such that the unit which was the stand-by unit becomes the active unit. In normal operation, both units will contain the same data and control information due to continuous updates of both units. Thus, a switch of the equipment from active to stand-by can be made without significant time delay or loss of information. Such duplication of equipment, while reliable, adds significantly to the cost of the system and an arrangement of equivalent reliability but requiring less than full duplication is desirable. Systems, such as multiprocessor configurations, have been suggested in the prior art which employ several "active" and one "stand-by" or spare unit to be called into operation in event of failure of one of the "active" units. Generally, such arrangements are not satisfactory in real time communications switching systems since a significant loss of data may result during the time required to activate a spare unit, particularly since control information which changes in time must be transferred to the spare unit.
In time-division switching systems such as described in the aforementioned Johnson et al., patent, PCM data words representing speech samples are received from a time-division transmission line in serial form, buffered and switched through a network in serial form. In another prior art arrangement disclosed in British Pat. No. 1,349,823, the data words are switched simultaneously in parallel paths. For example, an eight-bit word will simultaneously occupy eight switching paths, one switching path for each bit. For reliability, one additional path is provided for each eight-bit word which may be used as a spare path in the event of failure of one of the eight other paths. Such a parallel switching arrangement, however, is too costly to be practical in any large capacity switching system.